The invention relates to a logic full-adder circuit for adding two binary numbers a and b which each consist of n bits, n being a natural number larger than or equal to 2. The full adder comprises an inverting OR-gate and an inverting AND-gate for each bit a.sub.i, b.sub.i of the numbers a and b, where 0.ltoreq.i.ltoreq.n, said gates receiving the bit signals a.sub.i and b.sub.i in order to form an inverted OR-signal a.sub.i +b.sub.i and an inverted AND-signal a.sub.i .multidot.b.sub.i.
A summing circuit forms a sum signal s.sub.i from the bit signals a.sub.i and b.sub.i and an associated carry signal c.sub.i and/or the inverse c.sub.i thereof. The full-adder circuit also comprises a carry look-ahead signal circuit for generating a carry look-ahead signal c.sub.n+1 having the significance n+1 from all inverted OR-signals and AND-signals a.sub.i +b.sub.i and a.sub.i .multidot.b.sub.i where 0.ltoreq.i.ltoreq.n.
Such full-adder circuits are marketed in the form of integrated circuits by various firms, for example Signetics type SN 7483 or Motorola type MC14008. These circuits utilize the principle of forming a carry look-ahead signal from the carry signals produced during the various additions of bits of ascending significance. The carry look-ahead signal has the correct logic value for being applied to the adder gates of the bits of higher significance than the next-higher significance. If the bits of ascending significance of the signals a and b are successively denoted as a.sub.o, a.sub.1, a.sub.2 etc. and b.sub.o, b.sub.1, b.sub.2 etc. the carry signal c.sub.1 would, before the introduction of the carry look-ahead principle, have been formed from the addition a.sub.o +b.sub.b, said carry signal being applied to the adder gate of the signals a.sub.1 and b.sub.1, the carry signal c.sub.2 formed during this addition being subsequently applied to the adder gate of the signals a.sub.2 and b.sub.2 etc. so that the addition in the n.sup.th gate of the signals a.sub.n and b.sub.n could not be started before completion of the additions in all preceding gates. By generating the carry look-ahead signal c.sub.n in advance in some other way in accordance with the carry look-ahead principle, the speed of calculation can be substantially increased.
To this end, the known circuits utilize a separate arithmetic unit containing a truth table such that when the signals a.sub.o, a.sub.1 . . . a.sub.n-1 and b.sub.o, b.sub.1, . . . b.sub.n-1 are inputted, the output directly supplies the carry look-ahead signal c.sub.n. In order to generate the carry look-ahead signal, the signals a.sub.i +b.sub.i and a.sub.i .multidot.b.sub.i are generated by means of inverting OR-gates and AND-gates. In addition to this carry look-ahead signal circuit, a full-adder circuit comprise, for each bit of a binary number to be added, a summing circuit for generating a sum signal and a carry circuit for generating a carry signal which is required for obtaining the desired higher-order sum signal. It will be apparent that a substantial number of logic gates is required for this purpose.